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La Fonera (FON2100) Hardware Details
Just a couple days ago, Jordi Vallejo, CTO of FON, introduced the new La Fonera 2.0 (beta/developers edition) - watch it here on YouTube, which now comes with a 2nd ethernet port and a USB port. While we all wait for the Fonera 2.0 to arrive at our doorsteps, lets take another closer and more detailed look at the La Fonera 1.0 (2100) hardware.
Fonera
  • Power (socket for SK1)
    A drop-down regulator (AME1117), drops the input voltage from around 5V to 3.3V and (APL1117) 2.5V.
  • Flash Memory
    ST M25P64 serial flash, with a 50MHz SPI bus and 64Mbit capacity (8MByte), in 300mil SO16 format. SPI, slower than a parallel bus, potentially allows for adding additional memory devices to the bus.
    The flash memory is typically used with two different filesystems. I.e.: Squashfs, a compressed read-only filesystem for Linux and JFFS2, a log-structured file system designed for use on flash devices in embedded systems.
  • SDRAM
    Hynix HY57V281620E synchronous DRAM, 128Mbit organized in 16bit blocks, resulting in 16MByte.
  • Ethernet (RJ45 socket)
    Altima AC101 10/100 Mbit/s full duplex ethernet transceiver (placed on the flip-side of the PCB and running of a 25MHz crystal.
  • Wireless IEEE 802.11b / 802.11g (up to 54 Mbps)
    Atheros AR2315 single-chip WiFi processor running at 40 MHz.
    Integrated 32-bit MIPS R4000-class processor running at 183.5 MHz
  • Interfacing
    Serial (RS-232)
    Connecting the Fonera's serial port to a PC requires an TTL to RS-232 level shifter converting +3.3V and 0V to +12V and -12V.
    There is also a JTAG port on the PCB but ports pins are omitted. Fonera - JTAG connector

More Fonera photos can be found here: http://www.flickr.com/photos/wolfpaulus/tags/fonera/



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